periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 #include "cfg_timer_tim2.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
50 static const adc_conf_t adc_config[] = {
51  { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 4 }, /* ADC1_IN4, fast */
52  { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 6 }, /* ADC12_IN6, slow */
53  { .pin = GPIO_PIN(PORT_C, 3), .dev = 1, .chan = 9 }, /* ADC12_IN9, slow */
54  { .pin = GPIO_PIN(PORT_D, 11), .dev = 2, .chan = 8 }, /* ADC34_IN8, slow */
55  { .pin = GPIO_PIN(PORT_D, 12), .dev = 3, .chan = 9 }, /* ADC34_IN9, slow */
56  { .pin = GPIO_PIN(PORT_D, 13), .dev = 3, .chan = 10 }, /* ADC34_IN10, slo */
57 };
58 
59 #define ADC_NUMOF ARRAY_SIZE(adc_config)
60 
66 static const uart_conf_t uart_config[] = {
67  {
68  .dev = USART3,
69  .rcc_mask = RCC_APB1ENR_USART3EN,
70  .rx_pin = GPIO_PIN(PORT_D, 9),
71  .tx_pin = GPIO_PIN(PORT_D, 8),
72  .rx_af = GPIO_AF7,
73  .tx_af = GPIO_AF7,
74  .bus = APB1,
75  .irqn = USART3_IRQn,
76 #ifdef UART_USE_DMA
77  .dma_stream = 6,
78  .dma_chan = 4
79 #endif
80  },
81  {
82  .dev = USART1,
83  .rcc_mask = RCC_APB2ENR_USART1EN,
84  .rx_pin = GPIO_PIN(PORT_C, 5),
85  .tx_pin = GPIO_PIN(PORT_C, 4),
86  .rx_af = GPIO_AF7,
87  .tx_af = GPIO_AF7,
88  .bus = APB2,
89  .irqn = USART1_IRQn,
90 #ifdef UART_USE_DMA
91  .dma_stream = 5,
92  .dma_chan = 4
93 #endif
94  },
95  {
96  .dev = USART2,
97  .rcc_mask = RCC_APB1ENR_USART2EN,
98  .rx_pin = GPIO_PIN(PORT_D, 6),
99  .tx_pin = GPIO_PIN(PORT_D, 5),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB1,
103  .irqn = USART2_IRQn,
104 #ifdef UART_USE_DMA
105  .dma_stream = 4,
106  .dma_chan = 4
107 #endif
108  },
109 };
110 
111 #define UART_0_ISR (isr_usart3)
112 #define UART_0_DMA_ISR (isr_dma1_stream6)
113 #define UART_1_ISR (isr_usart1)
114 #define UART_1_DMA_ISR (isr_dma1_stream5)
115 #define UART_2_ISR (isr_usart2)
116 #define UART_2_DMA_ISR (isr_dma1_stream4)
117 
118 #define UART_NUMOF ARRAY_SIZE(uart_config)
119 
125 static const pwm_conf_t pwm_config[] = {
126  {
127  .dev = TIM1,
128  .rcc_mask = RCC_APB2ENR_TIM1EN,
129  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
130  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
131  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
132  { .pin = GPIO_UNDEF, .cc_chan = 0} },
133  .af = GPIO_AF2,
134  .bus = APB2
135  },
136  {
137  .dev = TIM4,
138  .rcc_mask = RCC_APB1ENR_TIM4EN,
139  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
140  { .pin = GPIO_UNDEF, .cc_chan = 0},
141  { .pin = GPIO_UNDEF, .cc_chan = 0},
142  { .pin = GPIO_UNDEF, .cc_chan = 0} },
143  .af = GPIO_AF2,
144  .bus = APB1
145  }
146 };
147 
148 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
149 
155 static const spi_conf_t spi_config[] = {
156  {
157  .dev = SPI1,
158  .mosi_pin = GPIO_PIN(PORT_A, 7),
159  .miso_pin = GPIO_PIN(PORT_A, 6),
160  .sclk_pin = GPIO_PIN(PORT_A, 5),
161  .cs_pin = GPIO_UNDEF,
162  .mosi_af = GPIO_AF5,
163  .miso_af = GPIO_AF5,
164  .sclk_af = GPIO_AF5,
165  .cs_af = GPIO_AF5,
166  .rccmask = RCC_APB2ENR_SPI1EN,
167  .apbbus = APB2
168  }
169 };
170 
171 #define SPI_NUMOF ARRAY_SIZE(spi_config)
172 
174 #ifdef __cplusplus
175 }
176 #endif
177 
178 #endif /* PERIPH_CONF_H */
179 
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
adc_conf_t::pin
gpio_t pin
pin to use
Definition: periph_cpu.h:343
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
cfg_timer_tim2.h
Common configuration for STM32 Timer peripheral based on TIM2.
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176