periph_conf.h
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1 /*
2  * Copyright (C) 2018 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* Add specific clock configuration (HSE, LSE) for this board here */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 #include "cfg_i2c1_pb8_pb9.h"
30 #include "cfg_rtt_default.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 static const timer_conf_t timer_config[] = {
41  {
42  .dev = TIM5,
43  .max = 0xffffffff,
44  .rcc_mask = RCC_APB1ENR1_TIM5EN,
45  .bus = APB1,
46  .irqn = TIM5_IRQn
47  }
48 };
49 
50 #define TIMER_0_ISR isr_tim5
51 
52 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
53 
59 static const uart_conf_t uart_config[] = {
60  {
61  .dev = LPUART1,
62  .rcc_mask = RCC_APB1ENR2_LPUART1EN,
63  .rx_pin = GPIO_PIN(PORT_G, 8),
64  .tx_pin = GPIO_PIN(PORT_G, 7),
65  .rx_af = GPIO_AF8,
66  .tx_af = GPIO_AF8,
67  .bus = APB12,
68  .irqn = LPUART1_IRQn,
69  .type = STM32_LPUART,
70  .clk_src = 0,
71  },
72  {
73  .dev = USART3,
74  .rcc_mask = RCC_APB1ENR1_USART3EN,
75  .rx_pin = GPIO_PIN(PORT_D, 9),
76  .tx_pin = GPIO_PIN(PORT_D, 8),
77  .rx_af = GPIO_AF7,
78  .tx_af = GPIO_AF7,
79  .bus = APB1,
80  .irqn = USART3_IRQn,
81  .type = STM32_USART,
82  .clk_src = 0, /* Use APB clock */
83 #ifdef UART_USE_DMA
84  .dma_stream = 6,
85  .dma_chan = 4
86 #endif
87  }
88 };
89 
90 #define UART_0_ISR (isr_lpuart1)
91 #define UART_1_ISR (isr_usart3)
92 
93 #define UART_NUMOF ARRAY_SIZE(uart_config)
94 
100 static const spi_conf_t spi_config[] = {
101  {
102  .dev = SPI1,
103  .mosi_pin = GPIO_PIN(PORT_A, 7),
104  .miso_pin = GPIO_PIN(PORT_A, 6),
105  .sclk_pin = GPIO_PIN(PORT_A, 5),
106  .cs_pin = GPIO_UNDEF,
107  .mosi_af = GPIO_AF5,
108  .miso_af = GPIO_AF5,
109  .sclk_af = GPIO_AF5,
110  .cs_af = GPIO_AF5,
111  .rccmask = RCC_APB2ENR_SPI1EN,
112  .apbbus = APB2
113  }
114 };
115 
116 #define SPI_NUMOF ARRAY_SIZE(spi_config)
117 
119 #ifdef __cplusplus
120 }
121 #endif
122 
123 #endif /* PERIPH_CONF_H */
124 
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu_common.h:94
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition: periph_cpu.h:583
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
STM32_LPUART
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: periph_cpu.h:584
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
PORT_G
@ PORT_G
port G
Definition: periph_cpu.h:42
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176