periph_conf.h
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1 /*
2  * Copyright (C) 2020 Scallog
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
43 static const adc_conf_t adc_config[] = {
44  { GPIO_PIN(PORT_C, 0), 0, 10 },
45  { GPIO_PIN(PORT_C, 1), 0, 11 },
46  { GPIO_PIN(PORT_C, 2), 0, 12 },
47  { GPIO_PIN(PORT_C, 3), 0, 13 },
48  { GPIO_PIN(PORT_C, 4), 0, 14 },
49  { GPIO_PIN(PORT_C, 5), 0, 15 }
50 };
51 
52 #define ADC_NUMOF ARRAY_SIZE(adc_config)
53 
59 static const pwm_conf_t pwm_config[] = {
60  {
61  .dev = TIM1,
62  .rcc_mask = RCC_APB2ENR_TIM1EN,
63  .chan = { { .pin = GPIO_PIN(PORT_A, 8), .cc_chan = 0 },
64  { .pin = GPIO_PIN(PORT_A, 9), .cc_chan = 1 },
65  { .pin = GPIO_PIN(PORT_A, 10), .cc_chan = 2 },
66  { .pin = GPIO_PIN(PORT_A, 11), .cc_chan = 3 } },
67  .af = GPIO_AF_OUT_PP,
68  .bus = APB2
69  },
70  {
71  .dev = TIM2,
72  .rcc_mask = RCC_APB1ENR_TIM2EN,
73  .chan = { { .pin = GPIO_PIN(PORT_A, 0), .cc_chan = 0 },
74  { .pin = GPIO_PIN(PORT_A, 1), .cc_chan = 1 },
75  { .pin = GPIO_PIN(PORT_A, 2), .cc_chan = 2 },
76  { .pin = GPIO_PIN(PORT_A, 3), .cc_chan = 3 } },
77  .af = GPIO_AF_OUT_PP,
78  .bus = APB1
79  },
80  {
81  .dev = TIM3,
82  .rcc_mask = RCC_APB1ENR_TIM3EN,
83  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
84  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 },
85  { .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
86  { .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
87  .af = GPIO_AF_OUT_PP,
88  .bus = APB1
89  },
90  {
91  .dev = TIM4,
92  .rcc_mask = RCC_APB1ENR_TIM4EN,
93  .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
94  { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 },
95  { .pin = GPIO_PIN(PORT_B, 8), .cc_chan = 2 },
96  { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 3 } },
97  .af = GPIO_AF_OUT_PP,
98  .bus = APB1
99  }
100 };
101 
102 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
103 
109 static const timer_conf_t timer_config[] = {
110  {
111  .dev = TIM2,
112  .max = 0x0000ffff,
113  .rcc_mask = RCC_APB1ENR_TIM2EN,
114  .bus = APB1,
115  .irqn = TIM2_IRQn
116  },
117  {
118  .dev = TIM3,
119  .max = 0x0000ffff,
120  .rcc_mask = RCC_APB1ENR_TIM3EN,
121  .bus = APB1,
122  .irqn = TIM3_IRQn
123  },
124  {
125  .dev = TIM4,
126  .max = 0x0000ffff,
127  .rcc_mask = RCC_APB1ENR_TIM4EN,
128  .bus = APB1,
129  .irqn = TIM4_IRQn
130  }
131 };
132 
133 #define TIMER_0_ISR isr_tim2
134 #define TIMER_1_ISR isr_tim3
135 #define TIMER_2_ISR isr_tim4
136 
137 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
138 
144 static const uart_conf_t uart_config[] = {
145  {
146  .dev = USART2,
147  .rcc_mask = RCC_APB1ENR_USART2EN,
148  .rx_pin = GPIO_PIN(PORT_A, 3),
149  .tx_pin = GPIO_PIN(PORT_A, 2),
150  .bus = APB1,
151  .irqn = USART2_IRQn
152  },
153  {
154  .dev = USART1,
155  .rcc_mask = RCC_APB2ENR_USART1EN,
156  .rx_pin = GPIO_PIN(PORT_A, 10),
157  .tx_pin = GPIO_PIN(PORT_A, 9),
158  .bus = APB2,
159  .irqn = USART1_IRQn
160  },
161  {
162  .dev = USART3,
163  .rcc_mask = RCC_APB1ENR_USART3EN,
164  .rx_pin = GPIO_PIN(PORT_B, 11),
165  .tx_pin = GPIO_PIN(PORT_B, 10),
166  .bus = APB1,
167  .irqn = USART3_IRQn
168  }
169 };
170 
171 #define UART_0_ISR (isr_usart2)
172 #define UART_1_ISR (isr_usart1)
173 #define UART_2_ISR (isr_usart3)
174 
175 #define UART_NUMOF ARRAY_SIZE(uart_config)
176 
182 #ifndef RTT_FREQUENCY
183 #define RTT_FREQUENCY (16384) /* in Hz */
184 #endif
185 
193 static const i2c_conf_t i2c_config[] = {
194  {
195  .dev = I2C1,
196  .speed = I2C_SPEED_NORMAL,
197  .scl_pin = GPIO_PIN(PORT_B, 8),
198  .sda_pin = GPIO_PIN(PORT_B, 9),
199  .bus = APB1,
200  .rcc_mask = RCC_APB1ENR_I2C1EN,
201  .clk = CLOCK_APB1,
202  .irqn = I2C1_EV_IRQn
203  },
204  {
205  .dev = I2C2,
206  .speed = I2C_SPEED_NORMAL,
207  .scl_pin = GPIO_PIN(PORT_B, 10),
208  .sda_pin = GPIO_PIN(PORT_B, 11),
209  .bus = APB1,
210  .rcc_mask = RCC_APB1ENR_I2C2EN,
211  .clk = CLOCK_APB1,
212  .irqn = I2C2_EV_IRQn
213  }
214 };
215 
216 #define I2C_0_ISR isr_i2c1_ev
217 #define I2C_1_ISR isr_i2c2_ev
218 
219 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
220 
226 static const spi_conf_t spi_config[] = {
227  {
228  .dev = SPI1,
229  .mosi_pin = GPIO_PIN(PORT_A, 7),
230  .miso_pin = GPIO_PIN(PORT_A, 6),
231  .sclk_pin = GPIO_PIN(PORT_A, 5),
232  .cs_pin = GPIO_UNDEF,
233  .rccmask = RCC_APB2ENR_SPI1EN,
234  .apbbus = APB2
235  },
236  {
237  .dev = SPI2,
238  .mosi_pin = GPIO_PIN(PORT_B, 15),
239  .miso_pin = GPIO_PIN(PORT_B, 14),
240  .sclk_pin = GPIO_PIN(PORT_B, 13),
241  .cs_pin = GPIO_UNDEF,
242  .rccmask = RCC_APB1ENR_SPI2EN,
243  .apbbus = APB1
244  }
245 };
246 
247 #define SPI_NUMOF ARRAY_SIZE(spi_config)
248 
250 #ifdef __cplusplus
251 }
252 #endif
253 
254 #endif /* PERIPH_CONF_H */
255 
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
i2c_conf_t::dev
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:247
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176