periph_conf.h
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1 /*
2  * Copyright (C) 2015 Lari Lehtomäki
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 #include "cfg_i2c1_pb8_pb9.h"
35 #include "cfg_timer_tim5.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 static const dma_conf_t dma_config[] = {
46  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
47  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
48  { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
49  { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
50  { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */
51  { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */
52 };
53 
54 #define DMA_0_ISR isr_dma2_stream3
55 #define DMA_1_ISR isr_dma2_stream2
56 #define DMA_2_ISR isr_dma1_stream4
57 #define DMA_3_ISR isr_dma1_stream3
58 #define DMA_4_ISR isr_dma1_stream5
59 #define DMA_5_ISR isr_dma1_stream0
60 
61 #define DMA_NUMOF ARRAY_SIZE(dma_config)
62 
68 static const uart_conf_t uart_config[] = {
69  {
70  .dev = USART2,
71  .rcc_mask = RCC_APB1ENR_USART2EN,
72  .rx_pin = GPIO_PIN(PORT_A, 3),
73  .tx_pin = GPIO_PIN(PORT_A, 2),
74  .rx_af = GPIO_AF7,
75  .tx_af = GPIO_AF7,
76  .bus = APB1,
77  .irqn = USART2_IRQn,
78 #ifdef MODULE_PERIPH_DMA
79  .dma = DMA_STREAM_UNDEF,
80  .dma_chan = UINT8_MAX,
81 #endif
82  },
83  {
84  .dev = USART1,
85  .rcc_mask = RCC_APB2ENR_USART1EN,
86  .rx_pin = GPIO_PIN(PORT_A, 10),
87  .tx_pin = GPIO_PIN(PORT_A, 9),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB2,
91  .irqn = USART1_IRQn,
92 #ifdef MODULE_PERIPH_DMA
93  .dma = DMA_STREAM_UNDEF,
94  .dma_chan = UINT8_MAX,
95 #endif
96  },
97  {
98  .dev = USART6,
99  .rcc_mask = RCC_APB2ENR_USART6EN,
100  .rx_pin = GPIO_PIN(PORT_A, 12),
101  .tx_pin = GPIO_PIN(PORT_A, 11),
102  .rx_af = GPIO_AF8,
103  .tx_af = GPIO_AF8,
104  .bus = APB2,
105  .irqn = USART6_IRQn,
106 #ifdef MODULE_PERIPH_DMA
107  .dma = DMA_STREAM_UNDEF,
108  .dma_chan = UINT8_MAX,
109 #endif
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_1_ISR (isr_usart1)
115 #define UART_2_ISR (isr_usart6)
116 
117 #define UART_NUMOF ARRAY_SIZE(uart_config)
118 
124 static const pwm_conf_t pwm_config[] = {
125  {
126  .dev = TIM2,
127  .rcc_mask = RCC_APB1ENR_TIM2EN,
128  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
129  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
130  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
132  .af = GPIO_AF1,
133  .bus = APB1
134  },
135 };
136 
137 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
138 
144 static const qdec_conf_t qdec_config[] = {
145  {
146  .dev = TIM3,
147  .max = 0xffffffff,
148  .rcc_mask = RCC_APB1ENR_TIM3EN,
149  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
150  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
151  .af = GPIO_AF2,
152  .bus = APB1,
153  .irqn = TIM3_IRQn
154  },
155  {
156  .dev = TIM4,
157  .max = 0xffffffff,
158  .rcc_mask = RCC_APB1ENR_TIM4EN,
159  .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
160  { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
161  .af = GPIO_AF2,
162  .bus = APB1,
163  .irqn = TIM4_IRQn
164  },
165 };
166 
167 #define QDEC_0_ISR isr_tim3
168 #define QDEC_1_ISR isr_tim4
169 
170 #define QDEC_NUMOF ARRAY_SIZE(qdec_config)
171 
177 static const spi_conf_t spi_config[] = {
178  {
179  .dev = SPI1,
180  .mosi_pin = GPIO_PIN(PORT_A, 7),
181  .miso_pin = GPIO_PIN(PORT_A, 6),
182  .sclk_pin = GPIO_PIN(PORT_A, 5),
183  .cs_pin = GPIO_PIN(PORT_A, 4),
184  .mosi_af = GPIO_AF5,
185  .miso_af = GPIO_AF5,
186  .sclk_af = GPIO_AF5,
187  .cs_af = GPIO_AF5,
188  .rccmask = RCC_APB2ENR_SPI1EN,
189  .apbbus = APB2,
190 #ifdef MODULE_PERIPH_DMA
191  .tx_dma = 0,
192  .tx_dma_chan = 3,
193  .rx_dma = 1,
194  .rx_dma_chan = 3,
195 #endif
196  },
197  {
198  .dev = SPI2,
199  .mosi_pin = GPIO_PIN(PORT_B, 15),
200  .miso_pin = GPIO_PIN(PORT_B, 14),
201  .sclk_pin = GPIO_PIN(PORT_B, 13),
202  .cs_pin = GPIO_PIN(PORT_B, 12),
203  .mosi_af = GPIO_AF5,
204  .miso_af = GPIO_AF5,
205  .sclk_af = GPIO_AF5,
206  .cs_af = GPIO_AF5,
207  .rccmask = RCC_APB1ENR_SPI2EN,
208  .apbbus = APB1,
209 #ifdef MODULE_PERIPH_DMA
210  .tx_dma = 2,
211  .tx_dma_chan = 0,
212  .rx_dma = 3,
213  .rx_dma_chan = 0,
214 #endif
215  },
216  {
217  .dev = SPI3,
218  .mosi_pin = GPIO_PIN(PORT_C, 12),
219  .miso_pin = GPIO_PIN(PORT_C, 11),
220  .sclk_pin = GPIO_PIN(PORT_C, 10),
221  .cs_pin = GPIO_UNDEF,
222  .mosi_af = GPIO_AF6,
223  .miso_af = GPIO_AF6,
224  .sclk_af = GPIO_AF6,
225  .cs_af = GPIO_AF6,
226  .rccmask = RCC_APB1ENR_SPI3EN,
227  .apbbus = APB1,
228 #ifdef MODULE_PERIPH_DMA
229  .tx_dma = 4,
230  .tx_dma_chan = 0,
231  .rx_dma = 5,
232  .rx_dma_chan = 0,
233 #endif
234  }
235 };
236 
237 #define SPI_NUMOF ARRAY_SIZE(spi_config)
238 
250 static const adc_conf_t adc_config[] = {
251  {GPIO_PIN(PORT_A, 0), 0, 0},
252  {GPIO_PIN(PORT_A, 1), 0, 1},
253  {GPIO_PIN(PORT_A, 4), 0, 4},
254  {GPIO_PIN(PORT_B, 0), 0, 8},
255  {GPIO_PIN(PORT_C, 1), 0, 11},
256  {GPIO_PIN(PORT_C, 0), 0, 10},
257 };
258 
259 #define ADC_NUMOF ARRAY_SIZE(adc_config)
260 
262 #ifdef __cplusplus
263 }
264 #endif
265 
266 #endif /* PERIPH_CONF_H */
267 
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu_common.h:94
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
dma_conf_t::stream
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: periph_cpu.h:443
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
cfg_timer_tim5.h
Common configuration for STM32 Timer peripheral based on TIM5.
qdec_conf_t::dev
TIM_TypeDef * dev
Timer used.
Definition: periph_cpu.h:567
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
qdec_conf_t
QDEC configuration.
Definition: periph_cpu.h:566
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: periph_cpu_common.h:92
dma_conf_t
DMA configuration.
Definition: periph_cpu.h:420
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176