periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 /* This board provides an LSE */
25 #ifndef CONFIG_BOARD_HAS_LSE
26 #define CONFIG_BOARD_HAS_LSE 1
27 #endif
28 
29 /* This board provides an HSE */
30 #ifndef CONFIG_BOARD_HAS_HSE
31 #define CONFIG_BOARD_HAS_HSE 1
32 #endif
33 
34 #include "periph_cpu.h"
35 #include "clk_conf.h"
36 #include "cfg_i2c1_pb8_pb9.h"
37 #include "cfg_rtt_default.h"
38 #include "cfg_timer_tim5.h"
39 #include "cfg_usb_otg_fs.h"
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
49 static const dma_conf_t dma_config[] = {
50  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
51  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
52 };
53 
54 #define DMA_0_ISR isr_dma2_stream3
55 #define DMA_1_ISR isr_dma2_stream2
56 
57 #define DMA_NUMOF ARRAY_SIZE(dma_config)
58 
64 static const uart_conf_t uart_config[] = {
65  {
66  .dev = USART3,
67  .rcc_mask = RCC_APB1ENR_USART3EN,
68  .rx_pin = GPIO_PIN(PORT_D, 9),
69  .tx_pin = GPIO_PIN(PORT_D, 8),
70  .rx_af = GPIO_AF7,
71  .tx_af = GPIO_AF7,
72  .bus = APB1,
73  .irqn = USART3_IRQn,
74 #ifdef MODULE_PERIPH_DMA
75  .dma = 0,
76  .dma_chan = 7,
77 #endif
78  },
79  {
80  .dev = USART6,
81  .rcc_mask = RCC_APB2ENR_USART6EN,
82  .rx_pin = GPIO_PIN(PORT_G, 9),
83  .tx_pin = GPIO_PIN(PORT_G, 14),
84  .rx_af = GPIO_AF8,
85  .tx_af = GPIO_AF8,
86  .bus = APB2,
87  .irqn = USART6_IRQn,
88 #ifdef MODULE_PERIPH_DMA
89  .dma = 1,
90  .dma_chan = 5,
91 #endif
92  },
93  {
94  .dev = USART2,
95  .rcc_mask = RCC_APB1ENR_USART2EN,
96  .rx_pin = GPIO_PIN(PORT_D, 6),
97  .tx_pin = GPIO_PIN(PORT_D, 5),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART2_IRQn,
102 #ifdef MODULE_PERIPH_DMA
103  .dma = 3,
104  .dma_chan = 4,
105 #endif
106  },
107 };
108 
109 #define UART_0_ISR (isr_usart3)
110 #define UART_1_ISR (isr_usart6)
111 #define UART_2_ISR (isr_usart2)
112 
113 #define UART_NUMOF ARRAY_SIZE(uart_config)
114 
120 static const pwm_conf_t pwm_config[] = {
121  {
122  .dev = TIM1,
123  .rcc_mask = RCC_APB2ENR_TIM1EN,
124  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
125  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
126  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
127  { .pin = GPIO_UNDEF, .cc_chan = 0} },
128  .af = GPIO_AF1,
129  .bus = APB2
130  },
131  {
132  .dev = TIM4,
133  .rcc_mask = RCC_APB1ENR_TIM4EN,
134  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
135  { .pin = GPIO_UNDEF, .cc_chan = 0},
136  { .pin = GPIO_UNDEF, .cc_chan = 0},
137  { .pin = GPIO_UNDEF, .cc_chan = 0} },
138  .af = GPIO_AF2,
139  .bus = APB1
140  },
141 };
142 
143 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
144 
150 static const spi_conf_t spi_config[] = {
151  {
152  .dev = SPI1,
153  .mosi_pin = GPIO_PIN(PORT_A, 7),
154  .miso_pin = GPIO_PIN(PORT_A, 6),
155  .sclk_pin = GPIO_PIN(PORT_A, 5),
156  .cs_pin = GPIO_PIN(PORT_A, 4),
157  .mosi_af = GPIO_AF5,
158  .miso_af = GPIO_AF5,
159  .sclk_af = GPIO_AF5,
160  .cs_af = GPIO_AF5,
161  .rccmask = RCC_APB2ENR_SPI1EN,
162  .apbbus = APB2,
163 #ifdef MODULE_PERIPH_DMA
164  .tx_dma = 0,
165  .tx_dma_chan = 3,
166  .rx_dma = 1,
167  .rx_dma_chan = 3,
168 #endif
169  }
170 };
171 
172 #define SPI_NUMOF ARRAY_SIZE(spi_config)
173 
185 static const adc_conf_t adc_config[] = {
186  {GPIO_PIN(PORT_A, 3), 0, 3},
187  {GPIO_PIN(PORT_C, 0), 0, 10},
188  {GPIO_PIN(PORT_C, 3), 0, 13},
189  {GPIO_PIN(PORT_C, 1), 0, 11},
190  {GPIO_PIN(PORT_C, 4), 0, 14},
191  {GPIO_PIN(PORT_C, 5), 0, 15},
192 };
193 
194 #define ADC_NUMOF ARRAY_SIZE(adc_config)
195 
201 #ifndef RTT_FREQUENCY
202 #define RTT_FREQUENCY (4096)
203 #endif
204 
206 #ifdef __cplusplus
207 }
208 #endif
209 
210 #endif /* PERIPH_CONF_H */
211 
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu_common.h:94
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
dma_conf_t::stream
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: periph_cpu.h:443
cfg_usb_otg_fs.h
Common configuration for STM32 OTG FS peripheral.
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
cfg_timer_tim5.h
Common configuration for STM32 Timer peripheral based on TIM5.
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
dma_conf_t
DMA configuration.
Definition: periph_cpu.h:420
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
PORT_G
@ PORT_G
port G
Definition: periph_cpu.h:42
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176