periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 #include "cfg_i2c1_pb8_pb9.h"
35 #include "cfg_timer_tim5.h"
36 #include "cfg_usb_otg_fs.h"
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
46 static const dma_conf_t dma_config[] = {
47  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
48  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
49 };
50 
51 #define DMA_0_ISR isr_dma2_stream3
52 #define DMA_1_ISR isr_dma2_stream2
53 
54 #define DMA_NUMOF ARRAY_SIZE(dma_config)
55 
61 static const uart_conf_t uart_config[] = {
62  {
63  .dev = USART3,
64  .rcc_mask = RCC_APB1ENR_USART3EN,
65  .rx_pin = GPIO_PIN(PORT_D, 9),
66  .tx_pin = GPIO_PIN(PORT_D, 8),
67  .rx_af = GPIO_AF7,
68  .tx_af = GPIO_AF7,
69  .bus = APB1,
70  .irqn = USART3_IRQn,
71 #ifdef MODULE_PERIPH_DMA
72  .dma = DMA_STREAM_UNDEF,
73  .dma_chan = UINT8_MAX,
74 #endif
75  },
76  {
77  .dev = USART6,
78  .rcc_mask = RCC_APB2ENR_USART6EN,
79  .rx_pin = GPIO_PIN(PORT_G, 9),
80  .tx_pin = GPIO_PIN(PORT_G, 14),
81  .rx_af = GPIO_AF8,
82  .tx_af = GPIO_AF8,
83  .bus = APB2,
84  .irqn = USART6_IRQn,
85 #ifdef MODULE_PERIPH_DMA
86  .dma = DMA_STREAM_UNDEF,
87  .dma_chan = UINT8_MAX,
88 #endif
89  },
90  {
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_D, 6),
94  .tx_pin = GPIO_PIN(PORT_D, 5),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB1,
98  .irqn = USART2_IRQn,
99 #ifdef MODULE_PERIPH_DMA
100  .dma = DMA_STREAM_UNDEF,
101  .dma_chan = UINT8_MAX,
102 #endif
103  },
104 };
105 
106 #define UART_0_ISR (isr_usart3)
107 #define UART_1_ISR (isr_usart6)
108 #define UART_2_ISR (isr_usart2)
109 
110 #define UART_NUMOF ARRAY_SIZE(uart_config)
111 
117 static const pwm_conf_t pwm_config[] = {
118  {
119  .dev = TIM1,
120  .rcc_mask = RCC_APB2ENR_TIM1EN,
121  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
122  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
123  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
124  { .pin = GPIO_UNDEF, .cc_chan = 0} },
125  .af = GPIO_AF1,
126  .bus = APB2
127  },
128  {
129  .dev = TIM4,
130  .rcc_mask = RCC_APB1ENR_TIM4EN,
131  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
132  { .pin = GPIO_UNDEF, .cc_chan = 0},
133  { .pin = GPIO_UNDEF, .cc_chan = 0},
134  { .pin = GPIO_UNDEF, .cc_chan = 0} },
135  .af = GPIO_AF2,
136  .bus = APB1
137  },
138 };
139 
140 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
141 
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = SPI1,
150  .mosi_pin = GPIO_PIN(PORT_A, 7),
151  .miso_pin = GPIO_PIN(PORT_A, 6),
152  .sclk_pin = GPIO_PIN(PORT_A, 5),
153  .cs_pin = GPIO_UNDEF,
154  .mosi_af = GPIO_AF5,
155  .miso_af = GPIO_AF5,
156  .sclk_af = GPIO_AF5,
157  .cs_af = GPIO_AF5,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2,
160 #ifdef MODULE_PERIPH_DMA
161  .tx_dma = 0,
162  .tx_dma_chan = 3,
163  .rx_dma = 1,
164  .rx_dma_chan = 3,
165 #endif
166  },
167 };
168 
169 #define SPI_NUMOF ARRAY_SIZE(spi_config)
170 
172 #ifdef __cplusplus
173 }
174 #endif
175 
176 #endif /* PERIPH_CONF_H */
177 
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu_common.h:94
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
dma_conf_t::stream
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: periph_cpu.h:443
cfg_usb_otg_fs.h
Common configuration for STM32 OTG FS peripheral.
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
cfg_timer_tim5.h
Common configuration for STM32 Timer peripheral based on TIM5.
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
dma_conf_t
DMA configuration.
Definition: periph_cpu.h:420
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
PORT_G
@ PORT_G
port G
Definition: periph_cpu.h:42
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176