periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an HSE */
23 #ifndef CONFIG_BOARD_HAS_HSE
24 #define CONFIG_BOARD_HAS_HSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 static const dac_conf_t dac_config[] = {
39  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 }
40 };
41 
42 #define DAC_NUMOF ARRAY_SIZE(dac_config)
43 
49 static const timer_conf_t timer_config[] = {
50  {
51  .dev = TIM2,
52  .max = 0xffffffff,
53  .rcc_mask = RCC_APB1ENR_TIM2EN,
54  .bus = APB1,
55  .irqn = TIM2_IRQn
56  }
57 };
58 
59 #define TIMER_0_ISR isr_tim2
60 
61 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
62 
68 static const uart_conf_t uart_config[] = {
69  {
70  .dev = USART1,
71  .rcc_mask = RCC_APB2ENR_USART1EN,
72  .rx_pin = GPIO_PIN(PORT_A, 10),
73  .tx_pin = GPIO_PIN(PORT_A, 9),
74  .rx_af = GPIO_AF7,
75  .tx_af = GPIO_AF7,
76  .bus = APB2,
77  .irqn = USART1_IRQn
78  },
79  {
80  .dev = USART2,
81  .rcc_mask = RCC_APB1ENR_USART2EN,
82  .rx_pin = GPIO_PIN(PORT_D, 6),
83  .tx_pin = GPIO_PIN(PORT_D, 5),
84  .rx_af = GPIO_AF7,
85  .tx_af = GPIO_AF7,
86  .bus = APB1,
87  .irqn = USART2_IRQn
88  },
89  {
90  .dev = USART3,
91  .rcc_mask = RCC_APB1ENR_USART3EN,
92  .rx_pin = GPIO_PIN(PORT_D, 9),
93  .tx_pin = GPIO_PIN(PORT_D, 8),
94  .rx_af = GPIO_AF7,
95  .tx_af = GPIO_AF7,
96  .bus = APB1,
97  .irqn = USART3_IRQn
98  }
99 };
100 
101 #define UART_0_ISR (isr_usart1)
102 #define UART_1_ISR (isr_usart2)
103 #define UART_2_ISR (isr_usart3)
104 
105 #define UART_NUMOF ARRAY_SIZE(uart_config)
106 
112 static const pwm_conf_t pwm_config[] = {
113  {
114  .dev = TIM3,
115  .rcc_mask = RCC_APB1ENR_TIM3EN,
116  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
117  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
118  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
119  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
120  .af = GPIO_AF2,
121  .bus = APB1
122  },
123  {
124  .dev = TIM4,
125  .rcc_mask = RCC_APB1ENR_TIM4EN,
126  .chan = { { .pin = GPIO_PIN(PORT_D, 12), .cc_chan = 0},
127  { .pin = GPIO_PIN(PORT_D, 13), .cc_chan = 1},
128  { .pin = GPIO_PIN(PORT_D, 14), .cc_chan = 2},
129  { .pin = GPIO_PIN(PORT_D, 15), .cc_chan = 3} },
130  .af = GPIO_AF2,
131  .bus = APB1
132  }
133 };
134 
135 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
136 
142 static const spi_conf_t spi_config[] = {
143  {
144  .dev = SPI1,
145  .mosi_pin = GPIO_PIN(PORT_A, 7),
146  .miso_pin = GPIO_PIN(PORT_A, 6),
147  .sclk_pin = GPIO_PIN(PORT_A, 5),
148  .cs_pin = GPIO_UNDEF,
149  .mosi_af = GPIO_AF5,
150  .miso_af = GPIO_AF5,
151  .sclk_af = GPIO_AF5,
152  .cs_af = GPIO_AF5,
153  .rccmask = RCC_APB2ENR_SPI1EN,
154  .apbbus = APB2
155  },
156  {
157  .dev = SPI3,
158  .mosi_pin = GPIO_PIN(PORT_C, 12),
159  .miso_pin = GPIO_PIN(PORT_C, 11),
160  .sclk_pin = GPIO_PIN(PORT_C, 10),
161  .cs_pin = GPIO_PIN(PORT_A, 15),
162  .mosi_af = GPIO_AF6,
163  .miso_af = GPIO_AF6,
164  .sclk_af = GPIO_AF6,
165  .cs_af = GPIO_AF6,
166  .rccmask = RCC_APB1ENR_SPI3EN,
167  .apbbus = APB1
168  }
169 };
170 
171 #define SPI_NUMOF ARRAY_SIZE(spi_config)
172 
178 static const i2c_conf_t i2c_config[] = {
179  {
180  .dev = I2C1,
181  .speed = I2C_SPEED_NORMAL,
182  .scl_pin = GPIO_PIN(PORT_B, 6),
183  .sda_pin = GPIO_PIN(PORT_B, 7),
184  .scl_af = GPIO_AF4,
185  .sda_af = GPIO_AF4,
186  .bus = APB1,
187  .rcc_mask = RCC_APB1ENR_I2C1EN,
188  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
189  .irqn = I2C1_ER_IRQn
190  },
191  {
192  .dev = I2C2,
193  .speed = I2C_SPEED_NORMAL,
194  .scl_pin = GPIO_PIN(PORT_F, 1),
195  .sda_pin = GPIO_PIN(PORT_F, 0),
196  .scl_af = GPIO_AF4,
197  .sda_af = GPIO_AF4,
198  .bus = APB1,
199  .rcc_mask = RCC_APB1ENR_I2C2EN,
200  .rcc_sw_mask = RCC_CFGR3_I2C2SW,
201  .irqn = I2C2_ER_IRQn
202  }
203 };
204 
205 #define I2C_0_ISR isr_i2c1_er
206 #define I2C_1_ISR isr_i2c2_er
207 
208 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
209 
211 #ifdef __cplusplus
212 }
213 #endif
214 
215 #endif /* PERIPH_CONF_H */
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: periph_cpu_common.h:90
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
dac_conf_t::pin
gpio_t pin
pin connected to the line
Definition: periph_cpu.h:519
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
PORT_F
@ PORT_F
port F
Definition: periph_cpu.h:41
dac_conf_t
DAC line configuration data.
Definition: periph_cpu.h:518
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: periph_cpu_common.h:92
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
i2c_conf_t::dev
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:247
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176