periph_conf.h
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1 /*
2  * Copyright (C) 2019 Benjamin Valentin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 /* This board provides an LSE */
26 #ifndef CONFIG_BOARD_HAS_LSE
27 #define CONFIG_BOARD_HAS_LSE 1
28 #endif
29 
30 /* This board provides an HSE */
31 #ifndef CONFIG_BOARD_HAS_HSE
32 #define CONFIG_BOARD_HAS_HSE 1
33 #endif
34 
35 /* The HSE provides a 25MHz clock */
36 #define CLOCK_HSE MHZ(25)
37 
38 #include "periph_cpu.h"
39 #include "clk_conf.h"
40 #include "cfg_i2c1_pb8_pb9.h"
41 #include "cfg_timer_tim5.h"
42 #include "cfg_usb_otg_fs.h"
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
52 static const uart_conf_t uart_config[] = {
53  {
54  .dev = USART2,
55  .rcc_mask = RCC_APB1ENR_USART2EN,
56  .rx_pin = GPIO_PIN(PORT_A, 3),
57  .tx_pin = GPIO_PIN(PORT_A, 2),
58  .rx_af = GPIO_AF7,
59  .tx_af = GPIO_AF7,
60  .bus = APB1,
61  .irqn = USART2_IRQn,
62 #ifdef MODULE_PERIPH_DMA
63  .dma = DMA_STREAM_UNDEF,
64  .dma_chan = UINT8_MAX,
65 #endif
66  },
67  {
68  .dev = USART1,
69  .rcc_mask = RCC_APB2ENR_USART1EN,
70  .rx_pin = GPIO_PIN(PORT_A, 10),
71  .tx_pin = GPIO_PIN(PORT_A, 9),
72  .rx_af = GPIO_AF7,
73  .tx_af = GPIO_AF7,
74  .bus = APB2,
75  .irqn = USART1_IRQn,
76 #ifdef MODULE_PERIPH_DMA
77  .dma = DMA_STREAM_UNDEF,
78  .dma_chan = UINT8_MAX,
79 #endif
80  },
81 };
82 
83 /* assign ISR vector names */
84 #define UART_0_ISR isr_usart2
85 #define UART_1_ISR isr_usart1
86 
87 /* deduct number of defined UART interfaces */
88 #define UART_NUMOF ARRAY_SIZE(uart_config)
89 
94 static const pwm_conf_t pwm_config[] = {
95  {
96  .dev = TIM2,
97  .rcc_mask = RCC_APB1ENR_TIM2EN,
98  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0 },
99  { .pin = GPIO_PIN(PORT_B, 3), /* D3 */ .cc_chan = 1 },
100  { .pin = GPIO_PIN(PORT_B, 10), /* D6 */ .cc_chan = 2 },
101  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
102  .af = GPIO_AF1,
103  .bus = APB1
104  },
105  {
106  .dev = TIM3,
107  .rcc_mask = RCC_APB1ENR_TIM3EN,
108  .chan = { { .pin = GPIO_PIN(PORT_B, 4), /* D5 */ .cc_chan = 0 },
109  { .pin = GPIO_PIN(PORT_C, 7), /* D9 */ .cc_chan = 1 },
110  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
111  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
112  .af = GPIO_AF2,
113  .bus = APB1
114  },
115 };
116 
117 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
118 
124 static const spi_conf_t spi_config[] = {
125  { /* U3 - SPI flash */
126  .dev = SPI1,
127  .mosi_pin = GPIO_PIN(PORT_A, 7),
128  .miso_pin = GPIO_PIN(PORT_A, 6),
129  .sclk_pin = GPIO_PIN(PORT_A, 5),
130  .cs_pin = GPIO_PIN(PORT_A, 4),
131  .mosi_af = GPIO_AF5,
132  .miso_af = GPIO_AF5,
133  .sclk_af = GPIO_AF5,
134  .cs_af = GPIO_AF5,
135  .rccmask = RCC_APB2ENR_SPI1EN,
136  .apbbus = APB2
137  },
138  {
139  .dev = SPI2,
140  .mosi_pin = GPIO_PIN(PORT_B, 15),
141  .miso_pin = GPIO_PIN(PORT_B, 14),
142  .sclk_pin = GPIO_PIN(PORT_B, 13),
143  .cs_pin = GPIO_PIN(PORT_B, 12),
144  .mosi_af = GPIO_AF5,
145  .miso_af = GPIO_AF5,
146  .sclk_af = GPIO_AF5,
147  .cs_af = GPIO_AF5,
148  .rccmask = RCC_APB1ENR_SPI2EN,
149  .apbbus = APB1
150  },
151  {
152  .dev = SPI3,
153  .mosi_pin = GPIO_PIN(PORT_B, 5),
154  .miso_pin = GPIO_PIN(PORT_B, 4),
155  .sclk_pin = GPIO_PIN(PORT_B, 3),
156  .cs_pin = GPIO_PIN(PORT_A, 15),
157  .mosi_af = GPIO_AF6,
158  .miso_af = GPIO_AF6,
159  .sclk_af = GPIO_AF6,
160  .cs_af = GPIO_AF6,
161  .rccmask = RCC_APB1ENR_SPI3EN,
162  .apbbus = APB1
163  },
164 };
165 
166 #define SPI_NUMOF ARRAY_SIZE(spi_config)
167 
178 static const adc_conf_t adc_config[] = {
179  {GPIO_PIN(PORT_A, 0), 0, 0},
180  {GPIO_PIN(PORT_A, 1), 0, 1},
181  {GPIO_PIN(PORT_A, 4), 0, 4},
182  {GPIO_PIN(PORT_B, 0), 0, 8},
183 };
184 
185 #define ADC_NUMOF ARRAY_SIZE(adc_config)
186 
188 #ifdef __cplusplus
189 }
190 #endif
191 
192 #endif /* PERIPH_CONF_H */
193 
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
cfg_usb_otg_fs.h
Common configuration for STM32 OTG FS peripheral.
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
cfg_timer_tim5.h
Common configuration for STM32 Timer peripheral based on TIM5.
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: periph_cpu_common.h:92
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176