periph_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 /* HSE available on this board */
24 #ifndef CONFIG_BOARD_HAS_HSE
25 #define CONFIG_BOARD_HAS_HSE 1
26 #endif
27 
28 /* This board provides an LSE */
29 #ifndef CONFIG_BOARD_HAS_LSE
30 #define CONFIG_BOARD_HAS_LSE 1
31 #endif
32 
33 #include "periph_cpu.h"
34 #include "f0/cfg_clock_default.h"
35 #include "cfg_i2c1_pb8_pb9.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 static const timer_conf_t timer_config[] = {
46  {
47  .dev = TIM1,
48  .max = 0x0000ffff,
49  .rcc_mask = RCC_APB2ENR_TIM1EN,
50  .bus = APB2,
51  .irqn = TIM1_CC_IRQn
52  }
53 };
54 
55 #define TIMER_0_ISR isr_tim1_cc
56 
57 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
58 
64 static const uart_conf_t uart_config[] = {
65  {
66  .dev = USART2,
67  .rcc_mask = RCC_APB1ENR_USART2EN,
68  .rx_pin = GPIO_PIN(PORT_A, 3),
69  .tx_pin = GPIO_PIN(PORT_A, 2),
70  .rx_af = GPIO_AF1,
71  .tx_af = GPIO_AF1,
72  .bus = APB1,
73  .irqn = USART2_IRQn
74  },
75  {
76  .dev = USART1,
77  .rcc_mask = RCC_APB2ENR_USART1EN,
78  .rx_pin = GPIO_PIN(PORT_A, 10),
79  .tx_pin = GPIO_PIN(PORT_A, 9),
80  .rx_af = GPIO_AF1,
81  .tx_af = GPIO_AF1,
82  .bus = APB2,
83  .irqn = USART1_IRQn
84  },
85  {
86  .dev = USART3,
87  .rcc_mask = RCC_APB1ENR_USART3EN,
88  .rx_pin = GPIO_PIN(PORT_C, 11),
89  .tx_pin = GPIO_PIN(PORT_C, 10),
90  .rx_af = GPIO_AF1,
91  .tx_af = GPIO_AF1,
92  .bus = APB1,
93  .irqn = USART3_8_IRQn
94  }
95 };
96 
97 #define UART_0_ISR (isr_usart2)
98 #define UART_1_ISR (isr_usart1)
99 #define UART_2_ISR (isr_usart3_8)
100 
101 #define UART_NUMOF ARRAY_SIZE(uart_config)
102 
108 static const pwm_conf_t pwm_config[] = {
109  {
110  .dev = TIM2,
111  .rcc_mask = RCC_APB1ENR_TIM2EN,
112  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
113  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
114  { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
115  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
116  .af = GPIO_AF2,
117  .bus = APB1
118  },
119  {
120  .dev = TIM3,
121  .rcc_mask = RCC_APB1ENR_TIM3EN,
122  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
123  { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
124  { .pin = GPIO_UNDEF, .cc_chan = 0 },
125  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
126  .af = GPIO_AF1,
127  .bus = APB1
128  },
129  {
130  .dev = TIM15,
131  .rcc_mask = RCC_APB2ENR_TIM15EN,
132  .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
133  { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
134  { .pin = GPIO_UNDEF, .cc_chan = 0 },
135  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
136  .af = GPIO_AF1,
137  .bus = APB2
138  }
139 };
140 
141 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
142 
148 static const spi_conf_t spi_config[] = {
149  {
150  .dev = SPI1,
151  .mosi_pin = GPIO_PIN(PORT_A, 7),
152  .miso_pin = GPIO_PIN(PORT_A, 6),
153  .sclk_pin = GPIO_PIN(PORT_A, 5),
154  .cs_pin = GPIO_PIN(PORT_A, 4),
155  .mosi_af = GPIO_AF0,
156  .miso_af = GPIO_AF0,
157  .sclk_af = GPIO_AF0,
158  .cs_af = GPIO_AF0,
159  .rccmask = RCC_APB2ENR_SPI1EN,
160  .apbbus = APB2
161  },
162  {
163  .dev = SPI2,
164  .mosi_pin = GPIO_PIN(PORT_B, 15),
165  .miso_pin = GPIO_PIN(PORT_B, 14),
166  .sclk_pin = GPIO_PIN(PORT_B, 13),
167  .cs_pin = GPIO_PIN(PORT_B, 12),
168  .mosi_af = GPIO_AF0,
169  .miso_af = GPIO_AF0,
170  .sclk_af = GPIO_AF0,
171  .cs_af = GPIO_AF0,
172  .rccmask = RCC_APB1ENR_SPI2EN,
173  .apbbus = APB1
174  },
175 };
176 
177 #define SPI_NUMOF ARRAY_SIZE(spi_config)
178 
184 static const adc_conf_t adc_config[] = {
185  { GPIO_PIN(PORT_A, 0), 0 },
186  { GPIO_PIN(PORT_A, 1), 1 },
187  { GPIO_PIN(PORT_A, 4), 4 },
188  { GPIO_PIN(PORT_B, 0), 8 },
189  { GPIO_PIN(PORT_C, 1), 11 },
190  { GPIO_PIN(PORT_C, 0), 10 }
191 };
192 
193 #define ADC_NUMOF ARRAY_SIZE(adc_config)
194 
196 #ifdef __cplusplus
197 }
198 #endif
199 
200 #endif /* PERIPH_CONF_H */
201 
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition: periph_cpu_common.h:154
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
cfg_clock_default.h
Default clock configuration for STM32F0.
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu_common.h:88
GPIO_AF0
@ GPIO_AF0
use alternate function 0
Definition: periph_cpu_common.h:86
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176